1. Field of the Invention
The present invention relates to a load driving device, and particularly to a load driving device which protects a high withstand voltage MOS transistor from ESD (Electro Static Discharge).
2. Description of the Related Art
FIG. 1 of the accompanying drawings is a circuit diagram representing a conventional load driving device. The load driving device has a power source pad 1 and a ground connection pad 2. The power source pad 1 and the ground connection pad 2 are connected to a power source line 3 and a ground connection line 4, respectively. An internal circuit 5 i.e., a load drive signal generator that performs logical calculation operations, is connected between the power source line 3 and the ground connection line 4. An output signal node SO of the internal circuit 5 is connected to a gate of a P-channel type MOS transistor 6 (called ‘PMOS’ hereinbelow) and a gate of an N-channel type MOS transistor 7 (called ‘NMOS’ hereinbelow) that constitutes an output buffer. The PMOS 6 and the NMOS 7 which are gate driven switching elements constitute an inverter having a push-pull configuration. Sources of the PMOS 6 and the NMOS 7 are connected to the power source line 3 and the ground connection line 4, respectively. A drain of the PMOS 6 functioning as an output node NO is connected through a protection resistor 11 to the drain of the NMOS 7, and connected through a protection resistor 12 to an output pad 8.
An anode and a cathode of a protection diode 13 are connected to the output pad 8 and the power source line 3, respectively. An anode and a cathode of a protection diode 14 are connected to the ground connection line 4 and the output pad 8, respectively. An NMOS 15 is connected between the power source line 3 and the ground connection line 4 so that the NMOS 15 performs a protection function between the power sources by its diode characteristic in a reverse direction. Such transistor is called as a power clamp transistor.
When an electrostatic surge which is higher than a power source voltage VDD is supplied to the output pad 8 in the load driving device having such a protection circuit, a magnitude of electric potential of the power source line 3 rises to a potential which is roughly equal to an electric potential of the output pad 8 because of an operation of a protection diode in a forward direction. Since, at this moment, a magnitude of voltage between the output pad 8 and the power source line 3 is limited by property of the protection diode 13 in the forward direction, an electrostatic breakdown of the PMOS 6 is avoided. When a magnitude of electric potential of the output pad 8 further rises to a higher potential by the electrostatic surge, a protection diode 14 and the NMOS 15 that performs a protection operation between the power and ground lines fall into breakdown, so that a magnitude of voltage of the output pad 8 and the ground connection line 4 drops rapidly. A magnitude of electric potential of the output pad 8 rises until the protection diode 14 or the NMOS 15 falls into breakdown. However, an electrostatic breakdown of the NMOS 7 can be avoided because a current flowing through the NMOS 7 is limited by the protection resistors 11 and 12 that are inserted in series to each other between the output pad 8 and the ground connection line 4. When an electrostatic surge that is lower than the ground potential is supplied to the output pad 8, an electrostatic breakdown of the PMOS 6 and the NMOS 7 can be avoided by the protection diode 14 which is biased forwardly and the protection resistors 11 and 12. Load driving devices which are known, for example, are disclosed in Japanese Laid Open No. 2004-71991, Japanese Laid Open No. H8-330521, Japanese Laid Open No. H11-274404, Japanese Patent No. 3386042, and Japanese Patent No. 3526853.
When an electrostatic surge is supplied across the output pad 8 and the ground connection pad 2, two surge current paths are formed. One of them is a path from the output pad 8 through the protection diode 13, the power source line 3, the NMOS 15, and the ground connection line 4, up to-the ground pad 2. The other is a path from the output pad 8 via the protection resistor 12, the protection resistor 11, the NMOS 7 and the ground connection line 4, up to the ground pad 2. Even though, the NMOS 15 has a characteristic which is similar to the NMOS 7, a breakdown of the NMOS 7 in the second surge current path may occur earlier, because an impedance of the power source line 3 and the ground connection line 4 in the first surge current path is large.
Thus, a value of the protection resistor 12 inserted between the output node NO and the output pad 8 must be so large that a current flowing through the NMOS 7 in the case of a breakdown of the NMOS 7 becomes smaller than the breakdown proof current. When, for example, a load circuit such as an organic electroluminescence display which is current drive-type circuit is connected to the conventional load driving device, a voltage drop appears across the protection resistor 12. Therefore, it is necessary to select a high power source voltage which necessitates usage of costly semiconductor devices. Further the protection resistor 12 consumes a useless power.
When a load circuit such as an organic electroluminescence display is driven at a voltage of, for example, 20 V or higher, it is necessary to use a high voltage proof MOS transistor in an output circuit. However, a magnitude of breakdown proof current against an electrostatic surge current closely relates to a gate width of the high voltage proof MOS transistor. Thus the gate width becomes huge to realize a necessary magnitude of breakdown proof current, and occupies a wide area of the element.